TL;DR: OpenTitan Earl Grey 2 introduces a standards-compliant I3C (Improved Inter-Integrated Circuit) block, a high-performance, flexible, low-power successor to the I2C bus. Offering both Controller and Target functionality, it delivers faster transfer speeds (up to 25Mbps) and enhanced reliability. Designed for cost-sensitive SoCs, this block achieves efficiency through a unique SCL-driven transceiver that enables operation at standard clock speeds, including support for Deep Sleep states.
Modern computing systems, from data centres to laptop and mobile phones, are constructed from multiple chips and there is a need for all of these chips to communicate with each other using only a few signals to reduce the cost of both the chips and the boards that connect them. The most common solution to this problem is a bus, and the industry-standard two-wire I2C bus is the most well-established implementation of such an architecture.
The I3C bus, standardised by the MIPI Alliance, is the natural successor to I2C and aims to provide those same advantages whilst overcoming the
limitations of I2C that have become apparent over its long lifetime.
The above diagram shows an example of an I3C bus and the ability to connect multiple Controllers and Targets using its ‘multi-drop design’ and just two wires.
I3C offers the following significant advantages:
- Speed: I2C is typically limited to 1Mbps. I3C raises the basic transfer speed to 12.5Mbps and supports 25Mbps via DDR signaling.
- Dynamic discovery of all devices: No address conflicts and no requirement for prior knowledge of the devices present.
- In-Band Interrupts (IBI): Interrupts are carried over the bus itself, without requiring additional, bespoke interrupt signals between devices.
- Hot-Join capability: Devices may connect and disconnect dynamically.
- Standardised command set for discovering device properties: Reduces the need for device-dependent code.
- Increased reliability: Parity and CRC-based error detection supports more robust communication between devices.
- Supports a larger number of devices via bridging and routing, without reducing the transfer speeds.
The OpenTitan project introduces an I3C block which provides the above advantages, offering both Controller and Target functionality whilst keeping the power consumption low by being designed to operate on lower clock frequencies. The IP block implements both Single Data Rate (SDR) signaling at 12.5MHz and Double Data Rate (HDR-DDR) at 25MHz, achieving the maximum possible throughput in these modes.
Support for entry into a Deep Sleep state is included, during which almost all of the IP block may be powered down, leaving only a tiny amount of logic remaining active. This logic is clocked directly from the I3C bus, awaiting a ‘Target Reset’ pattern from the Controller, instructing it to awaken.
The OpenTitan I3C block
Shown below is a block diagram of the design of the OpenTitan I3C block.
Design Challenges
Clock frequency and power consumption
Implementing I3C within an OpenTitan Root Of Trust (RoT) discrete chip presented some unique challenges. The RoT is a very cost-sensitive, small SoC that must have lower power consumption for mobile devices.
Most other I3C implementations rely upon an approach called ‘oversampling’ and an accurate, high frequency oscillator when capturing the I3C traffic. The use of higher frequencies means that the hardware designer has much more freedom in the implementation of the logic and many more cycles to capture and store the data. However, it also means higher power consumption, and the highest clock frequency used in any discrete OpenTitan SoC data is just 100MHz, with the peripherals typically operating on a 24MHz, 48MHz or 96MHz clock whilst other I3C implementations typically employ frequencies of 140MHz or more. The aim was to design an I3C implementation that could be used within the existing, or slightly-modified, clocking scheme and yet still be capable of achieving the full 25Mbps signalling offered by HDR-DDR (Double Data Rate) mode.
It quickly became apparent that by the time the Target has detected a transition on the Serial Clock (SCL) line and presented new data on the Serial Data (SDA) line it would be too late in returning the next data bit to the Controller, so an alternative approach had to be found.
Instead of sampling the SCL input and detecting transitions on that signal, as other I3C Target implementations do, the OpenTitan I3C Target uses the SCL signal of the controller to drive a small amount of its transceiver logic directly. This logic is sufficient to capture and transmit data words, whilst the bulk of the Target logic remains on the stable, continuously-running clock of the IP block.
Data reception and transmission is achieved using a shift register to convert between the serial data on SDA and the parallel data words transferred from and to the core logic. Furthermore, since HDR-DDR transfers data on both edges of the SCL signal, there are in fact two shift registers performing this conversion; one is clocked on the rising (positive) edge of SCL, and the other on the falling (negative edge).
Using this alternative clocking scheme for the Target-side logic allows the IP block to employ a clock frequency as low as 50MHz where power saving is paramount, but the design remains sufficiently flexible that clock frequencies up to 200MHz may also be accommodated. Careful design ensures that correct operation within the strict timing constraints of the I3C bus is attainable at a number of intermediate frequencies.
Read transfers
Using SCL directly resolves the turnaround response time without demanding a high frequency clock, but there remain issues with transferring data to and from the rest of the IP block, most notably CDCs (Clock Domain Crossings). A CDC means that data is transferred from logic operating in one clock domain to another clock domain with no defined relationship to the original frequency; failure to design for this will lead to an unreliable design. A standard solution to this is to use a two stage synchroniser but this adds significant delay in each direction and, in I3C’s case, this would mean not being able to respond to bus transactions in time.
Here the solution was to employ aggressive prefetching throughout the design for read data. In anticipation of data being required in response to a read request it is prefetched and made available to the logic running on the I3C SCL signal. It is then available immediately when a request is received.
Sleep states
OpenTitan discrete SoCs are also required to be able to enter sleep states, stopping clocks and/or removing the power supply to much of the design. With a protocol specification such as USB it is relatively trivial to awaken from a sleep state because the link is point-to-point and the USB protocol specification affords a generous 20ms to awaken and be ready to resume communication.
However the I3C bus is a true ‘multidrop’ bus, meaning that it runs to multiple devices and the traffic being sent to any one device is also presented to all other devices. This means that an SoC device attempting to enter a deep sleep state is subject to – and worse – must monitor all activity on the bus in order to detect when the Active Controller sends the special ‘Target Reset’ pattern. A ‘Target Reset’ pattern may be used to inform a sleeping device to awaken, but clearly it would be undesirable to have a large quantity of logic powered and operating on a high frequency clock whilst the RoT is supposed to be in a sleep state.
OpenTitan’s I3C implementation addresses this by having a small amount of dedicated logic that is driven directly by the 12.5MHz SCL signal, with the sole purpose of detecting this special pattern and instructing the SoC’s power management to awaken the chip.
The SoC thus remains responsive to the Controller whilst maintaining very low power consumption when it is inactive and sleeping.
Conclusion
The OpenTitan project has developed a standards compliant I3C Controller and Target block with standard HCI and TCRI interfaces for firmware. The compact design is modular, low power and designed to be portable.
About OpenTitan and lowRISC
Founded in 2014 at the University of Cambridge, lowRISC C.I.C. is a not-for-profit company that provides a neutral home for collaborative engineering to develop and maintain open-source silicon designs and tools for the long term. The lowRISC open-source silicon ecosystem includes the OpenTitan project, the world’s most active and widely adopted open-source silicon project, containing commercial-grade IP blocks and security certified hardware Root of Trust designs.
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