Earl Grey Discrete Root of Trust
Earl Grey is an open source, royalty free and permissively licensed design for a discrete Root of Trust chip, implemented as a top level in the OpenTitan® project. It can be used to implement the full Trusted Platform Module (TPM) specification
Earl Grey-based chips are in production by Nuvoton and shipping in Chromebooks as their security foundation, which demonstrates the quality and security credentials of the design. Earl Grey is designed to achieve security certification, and existing partners have achieved Common Criteria EAL5+ with it.
Technical details
Ibex® CPU
In dual-core locked step configuration with Enhanced Physical Memory Protection (ePMP). Its security features include:
- Low-latency memory scrambling on the instruction cache and path to OTP, Flash, ROM and SRAM
- Data independent timing
- Dummy instruction insertion
- Bus and register file integrity
- Hardened program counter
Security IP
Including AES, HMAC, KMAC, CSRNG, key manager and a programmable big number accelerator for RSA and ECC (OTBN). In addition, OpenTitan features system-level security features such as a manufacturing life cycle manager and an alert handler for handling critical security events.
Software
- Boot ROM code implementing secure boot and chip configuration
- Bare metal top-level tests
- SCA and FI hardened Crypto Library with accelerated standard algorithms like AES, KMAC, HMAC, SHA, ECC, RSA, and more
- SPHINCS+ PQC-secure boot using a stateless hash-based signatures scheme
Block Diagram
Use cases for Earl Grey
Using a discrete hardware RoT device is a good option when protection against physical attacks is required:
- They are security hardened not only in the RTL and software, but also with analog countermeasures
- They leverage the security expertise of a dedicated chip design team, so you do not need to build it in-house, and their security certification efforts
- They provide secure storage, which is required for some secure services such as mobile payments
By being open source, Earl Grey provides transparency in its implementation, so OEMs and end users can use it with confidence in the quality of its implementation.
Roadmap: Earl Grey 2
An Earl Grey 2 top level is currently under development to address the new security challenges introduced by Artificial Intelligence and future quantum computers:
- Hardware memory safety through the addition of Capability Hardware Enhanced RISC Instructions (CHERI), specifically CHERIoT
- Security-hardened and optimized Post-Quantum Cryptography (PQC) compatible with CNSA 2.0, through extensions to its crypto accelerators
- Advanced control plane I/O with the addition of an I3C controller and target to address peripheral bottlenecks
- Greater efficiency, reducing area and power consumption through process node updates, compressed instructions, IP block optimizations and power domain splitting
By being open source, Earl Grey provides transparency in its implementation, so OEMs and end users can use it with confidence in the quality of its implementation.
OpenTitan roadmap
lowRISC and other OpenTitan members continue to invest in the OpenTitan project. During 2026 and 2027 we are actively working on new features, including enhanced post-quantum cryptography (PQC) capabilities, new peripheral interfaces such as I3C, support for smaller process nodes and several other enhancements.
We are also running other open-source projects such as COSMIC to create new IP and improve the quality and efficiency of our products and processes. The outputs of these projects will benefit OpenTitan in the future. Our roadmaps are based on interest from existing and potential partners. If you would like to help steer the future direction of OpenTitan, contact us.
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