Integrated Roots of Trust
Darjeeling and Peppermint
Darjeeling
Technical details
Ibex® CPU
In dual-core locked step configuration with Enhanced Physical Memory Protection (ePMP). Its security features include:
- Low-latency memory scrambling on the instruction cache and path to OTP, Flash, ROM and SRAM
- Data independent timing
- Dummy instruction insertion
- Bus and register file integrity
- Hardened program counter
Security IP
Including AES, HMAC, KMAC, CSRNG, key manager and a programmable big number accelerator for RSA and ECC (OTBN). In addition, OpenTitan features system-level security features such as a manufacturing life cycle manager and an alert handler for handling critical security events.
Software
- Boot ROM code implementing secure boot and chip configuration
- Bare metal top-level tests
- SCA and FI hardened Crypto Library with accelerated standard algorithms like AES, KMAC, HMAC, SHA, ECC, RSA, and more
- SPHINCS+ PQC-secure boot using a stateless hash-based signatures scheme
Block Diagram
Darjeeling block diagram
Use cases for Darjeeling
An integrated hardware RoT enables the cost-effective addition of a secure element to an SoC to handle cryptographic operations.
There are multiple use cases for using an integrated RoT, including the following:
- When the silicon vendor has the security expertise to implement analogue countermeasures themselves
- When hardware attacks are not a concern – e.g. if the product would be destroyed while trying to access it
- In systems with multiple SoCs, where a discrete RoT provides the security foundation for the whole system, while each SoC is responsible for its own software attestation
By being open source, Darjeeling provides transparency in its implementation, so OEMs and end users can use it with confidence in the quality of its implementation.
Peppermint
The Peppermint top level is currently under development.
Peppermint has been developed as an integrated RoT for small devices such as wearables, which require a small, low-power implementation for secure boot.
Peppermint is smaller than Darjeeling, as it relies on the peripheral controllers and non-volatile memory controllers on the main SoC. In addition, it implements an always-on power and clock domain to be able to put most of the system in power-down mode when not used.
Peppermint implements security-hardened and optimized Post-Quantum Cryptography (PQC) compatible with CNSA 2.0, through extensions to its crypto accelerators.
Block Diagram
OpenTitan roadmap
lowRISC and other OpenTitan members continue to invest in the OpenTitan project. During 2026 and 2027 we are actively working on new features, including enhanced post-quantum cryptography (PQC) capabilities, new peripheral interfaces such as I3C, support for smaller process nodes and several other enhancements.
We are also running other open-source projects such as COSMIC to create new IP and improve the quality and efficiency of our products and processes. The outputs of these projects will benefit OpenTitan in the future. Our roadmaps are based on interest from existing and potential partners. If you would like to help steer the future direction of OpenTitan, contact us.
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