Ibex CPU

Ibex® is a small and highly configurable open-source RISC-V embedded processor available under an Apache 2.0 licence. It is formally verified and very well validated, and it has excellent toolchain integration, which has led many companies to use it in their commercial SoCs. 

Ibex was initially developed as part of the PULP platform under the name zero-riscy, and was contributed to lowRISC, who maintains it and develops it further.

Ibex has been hardened against fault injection and side channel attacks. This makes it ideal as a secure processor, and also highly suitable for many industrial, automotive, IoT and consumer applications where power and cost matter.

Ibex is the main CPU in the OpenTitan® root of trust, which has brought the quality of the design and documentation to new heights.

Technical details

Ibex supports the RISC-V Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), Bit Manipulation (B), and Code Size Reduction (Zcb, Zcmp) extensions. It is an in-order core with 2-3 pipeline stages, and has an optional instruction cache implementation for improved performance.

Since it is highly parametrizable, Ibex can achieve multiple performance and area/cost targets, with a maximum performance of 3.13 CoreMarks/Mhz and minimal area of 15 kGates. Our partners have demonstrated it running at up to 1 GHz in modern process nodes.

Getting started with Ibex

You can evaluate and get started with Ibex with the Ibex Demo System and an off-the-shelf FPGA board like Sonata.

We also provide the Ibex Simple System to easily evaluate and benchmark Ibex on Verilator.

At the moment there are no off-the-shelf microcontrollers or low-cost evaluation boards providing open access to an internal Ibex processor for software development.

Memory safety and CHERIoT-Ibex

The exploitation of memory vulnerabilities is a very common route of attack against software.

At lowRISC® we believe that the best approach to protecting your system against this type of attack is by taking a multi-pronged approach: improving the quality of your software with static analysis tools or through the adoption of memory-safe languages, and adding extra defenses in the hardware itself.

RISC-V processors can incorporate memory safety in hardware through the addition of the powerful Capability Hardware Enhanced RISC Instructions (CHERI). The CHERIoT-Ibex core implements a smaller, optimized version of CHERI specifically designed for low-cost embedded and IoT systems.

lowRISC worked with Microsoft on the verification of CHERIoT-Ibex, using both traditional and formal methods. CHERIoT-Ibex is an open-source Microsoft design, which is based on Ibex and inherits many of its benefits.

Our Sonata® board can be used to synthesize an example SoC design based on CHERIoT-Ibex on an FPGA. It enables the evaluation of CHERIoT-Ibex as a CPU and CHERI as a technology.

Ibex roadmap

We continue to invest in Ibex, implementing new extensions to the RISC-V architecture and adding new capabilities.

We are particularly interested in bringing memory safety as an officially supported feature in Ibex, and creating documentation for certification against functional safety (FuSa) standards. 

Our roadmaps are based on interest from existing and potential partners. If you would like to help steer the future direction of Ibex, contact us.