By Wei Song

Release version 0.2 (12-2015)


lowRISC is a not-for-profit organisation whose goal is to produce a fully open source System-on-Chip (SoC) in volume. We are building upon RISC-V processor core implementations from the RISC-V team at UC Berkeley. We will produce a SoC design to populate a low-cost community development board and to act as an ideal starting point for derivative open-source and commercial designs.

This tutorial introduces a standalone implementation of the Rocket chip. The original Rocket chip relies on a companion processor for accessing peripheral devices and I/O. This design replaces the companion processor with actual peripheral devices on FPGA providing an ‘untethered’ SoC that is able to boot a RISC-V Linux. A demo is provided using either a Xilinx Kintex-7 KC705 evaluation kit or a low-end Nexys™4 DDR Artix-7 FPGA Board.

Please note that this release is based on recent upstream Rocket-chip sources and therefore it does not currently include the tagged memory support provided in our previous release. We plan to re-integrate tagged memory support with additional optimisations in the early half of next year.

The tutorial also acts as an introduction to the RISC-V tools and provides a step-by-step guide to setting up the environment necessary to run test programs either in simulation or on an FPGA.


  1. Overview of the Rocket chip
  2. The development environment
  3. Simulations and FPGA Demo
  4. Release notes

Other useful sources of information


Many thanks to the RISC-V team at Berkeley for all their support and guidance. Special thanks to Krste Asanović, Scott Beamer, Christopher Celio, Henry Cook, Yunsup Lee, and Andrew Waterman for fielding numerous questions from us about the implementation details of the Rocket core and chip.

Also thanks to Stefan Wallentowitz who has provided advice for this release.