By Jonathan Kimmitt (also see acknowledgements below)

Release version 0.6 (10-2018)


lowRISC is a not-for-profit organisation whose goal is to produce a secure, flexible, and fully open source System-on-Chip (SoC). We are building upon RISC-V processor core implementations from the RISC-V team at UC Berkeley. This aims to be the ideal starting point for derivative open source and commercial designs.

This tutorial adds further functionality towards the final SoC design:

  • An eight packet buffer for Ethernet reception.
  • Bare-metal GDB debugging over JTAG without any extra hardware.
  • Processor speed doubled to 50MHz.
  • Colour Console with proper PC-compatible keyboard events.
  • Ethernet boot-loader DHCP support, ten times faster boot-loading.
  • SD-Card boot-loader comprehensive card detection base on u-boot.
  • Platform-level interrupt controller support.
  • All peripheral data paths 64-bit width.
  • Latest RISCV-kernel and Debian userland with advanced package tool.

The build environment and pre-built images support the same platform as the previous releases, a competitively priced Nexys™4 DDR Artix-7 FPGA Board.

Function Tagged-v0.1 Untethered-v0.2 Debug-v0.3 Minion-v0.4 Ethernet-v0.5 Refresh-v0.6
Rocket Priv. Spec. ? ? 1.7 nearly 1.91 nearly 1.91 1.10
Tagged memory * * *
untethered operation * * * optional *
SD card tethered SPI SPI SD SD SD
UART console tethered standard standard/trace standard/trace/VGA standard/VGA standard/VGA
PS/2 keyboard * * *
Minion Core *
Kernel md5 boot check * * *
PC-free operation * * *
Remote booting * *
Multiuser operation * *
Compressed instructions *
Debian binary compatible *


  1. Release notes
  2. Getting started with binary releases
  3. Index of development documentation
  4. Frequently asked questions

Work planned / In progress / TO DO

  • Optimising card transfer speed / Implementing multi-block transfers.
  • Offloading SD-card acceleration and Video scrolling to Minion.


Other useful sources of information