Tutorial for the debug preview of lowRISC
By Stefan Wallentowitz and Wei Song
Release version 0.3 (07-2016)
lowRISC is a not-for-profit organisation whose goal is to produce a fully open source System-on-Chip (SoC) in volume. We are building upon RISC-V processor core implementations from the RISC-V team at UC Berkeley. We will produce a SoC design to populate a low-cost community development board and to act as an ideal starting point for derivative open-source and commercial designs.
This tutorial adds further functionality towards the final SoC design by adding a debug infrastructure. It contains a technology preview of what we plan and gives some background on the trace debugging techniques. A demo is provided using a low-end Nexys™4 DDR Artix-7 FPGA Board.