System IP
The OpenTitan project includes a number of high-quality system IP blocks suitable for a wide range of applications.
- Support for multiple bus hosts and bus devices, with 32-bit and 64-bit widths and flexible address widths
- Support for multiple clock domains and outstanding requests
- Extendability for security features
- Reference designs for ROM and SRAM controllers
- 64-bit or 32-bit timer that can function as a wake-up or watchdog timer
- 12-bit prescaler to enable very long timeouts
- Two thresholds, to generate an interrupt or reset the core
- Support for 3 bus interfaces: two 32-bit TileLink interfaces and one 64-bit custom interface
- Transfer Modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory
- Support for 1-, 2- and 4-byte data transfers
- Fixed or incrementing address, with or without wrapping buffers
- Hardware handshake mode and interrupt generation
- Control for read, program and erase of Flash memory
- Support for accessing multiple types of information partition
- Parameterized support for burst program / read, up to 64B
- Flash memory protection at page boundaries
- RISC-V Platform-Level Interrupt Controller (PLIC) compliant interrupt controller
- Support for arbitrary number of interrupt vectors (up to 1023) and targets
- The mailbox implementation adopts the PCIe specification defined Data Object Exchange (DOE) mailbox protocol.
- Inbox and Outbox traffic restricted to firmware-specified address ranges for single physical RAM sharing.
- Interrupt-based signaling, with configurable maximum request and response message lengths.
- Flow control/back-pressure mechanism, with automatic detection and reporting of error conditions.
- Cold boot, low power entry / exit and reset support.
- 2 different low power modes.
- Software initiated low power entry and hardware requested low power exit.
- Peripheral reset requests.
- Low power abort and low power fall-through support.
- ROM integrity check at power-up. Local checks for escalator and power stability.
- JTAG Test Access Port (TAP).
- Run-control debug features (in cooperation with the CPU core), including breakpoints, single-stepping through code, and reading core registers.
- System Bus Access (SBA) through JTAG.
- Optional connection to a SoC Debug Access Control module (as in OpenTitan) to prevent or authenticate a debugger connection to the SoC.
- 64-bit timer with 12-bit prescaler and 8-bit step register.
- Compliant with RISC-V privileged specification v1.11.
- Configurable number of timers per hardware thread (hart) and number of harts.
Consultancy and support services
lowRISC® offers consultancy and technical support for all of this IP. If you would like us to implement new system components, modify existing ones or help you integrate them in your SoC and software stack, contact us.
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