Peripheral IP
As part of the OpenTitan project lowRISC and its partners created a number of peripheral IP blocks suitable for a wide range of applications.
All these IP blocks have been verified as part of the OpenTitan Earl Grey chip design, and are shipping in commercial devices.
- Low power, dual channel ADC, 10-bit output.
- 8 filters and debounce timers on the filter output.
- Support for sleep mode through slow always-on-clock.
- 32 GPIO ports.
- Configurable interrupt per GPIO for detecting rising edge, falling edge, or active low/high input.
- Two ways to update GPIO output: direct-write and masked (thread-safe) update.
- Support for I2C Controller and I2C Target device modes.
- Standard-mode (100 Kbaud), Fast-mode (400 Kbaud) and Fast-mode Plus (1 Mbaud).
- Support for all “Mandatory” features as specified for I2C Controllers (as per I2C specification revision 6), plus clock stretching and multi-controller features.
- Efficient software interface through queues and programmable interrupts.
- This module creates configurable output pattern on a data pin based on an independent clock, which can be divided by a 32-bit pre-divider
- Patterns of up to 64 bits, repeated up to 1024 times.
- Efficient software interface through queues and programmable interrupts.
- Configurable number of chip bidirectional IOs and peripheral inputs and outputs.
- Programmable control of chip pad attributes like output drive-strength, pull-up, pull-down and virtual open-drain.
- Programmable sleep mode behavior and pattern detectors to detect wakeup conditions.
- Support for life-cycle-based JTAG (TAP) isolation and muxing.
- Suitable for general-purpose use, but primarily designed for control of tri-color LEDs.
- Parameterizable number of output channels.
- Independent control of duty cycle, phase, polarity, step size and step frequency for all channels.
- PWM operation can continue in a low-power state.
- Support for SPI serial Flash emulation.
- Support for SPI Passthrough to a Flash memory, with address translation and filtering of inadmissible commands (256-bit filter CSR).
- Support for Trusted Platform Module (TPM) mode in conformance with the TPM PC Client Platform.
- Hardware control for remote devices using SPI, primarily designed for serial NOR Flash devices.
- Support for Standard SPI, Dual SPI or Quad SPI commands.
- Support for all SPI polarity and phases (CPOL, CPHA).
- Additional support for “Full-cycle” SPI transactions, wherein data can be read a full SPI Clock cycle after the active edge.
- 2-pin full duplex external interface with programmable baud rate.
- 64 x 8b RX buffer, 32 x 8b TX buffer.
- Interrupt for transmit empty, receive overflow, frame error, parity error, break error, and receive timeout.
- USB 2.0 Full-Speed (12 Mbps) Device interface .
- Complete implementation all the way down to the physical layer, with support for multiple USB PHYs or regular 3.3V IO pads for FPGA prototyping.
- Configurable up to 12 endpoints.
- Support for USB packet sizes up to 64 bytes.
- Support SETUP, IN and OUT transactions.
- Support for Bulk, Control, Interrupt and Isochronous endpoints and transactions.
- Streaming is possible through software.
Peripheral IP roadmap
We are currently working on a MIPI-compliant I3C implementation, supporting I3C Controller (Primary and Secondary) and I3C Target, single and double data rates.
Our roadmaps are based on interest from existing and potential partners. If you would like to help steer the future direction of our products, contact us.
Consultancy and support services
lowRISC offers consultancy and technical support for all of this IP. If you would like us to implement new peripherals, modify existing ones or help you integrate them in your SoC and software stack, contact us.
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