The lowRISC 0.6 milestone release is now available. This release includes an updated version of the Rocket RISC-V core, a higher core clock frequency, JTAG debugging support, Ethernet improvements, and more. See the release notes, for full details. We’ve also taken the opportunity to re-organise our documentation, adding an easy to follow quick-start guide.

Our next development focus is to add support for dropping in the Ariane RISC-V design (from ETH Zurich) as an alternative to Rocket.

Please report any issues on our GitHub repository, or discuss on our mailing list. As always, thank you to everyone who has contributed in any way – whether it’s advice and feedback, bug reports, code, or ideas. With special thanks to Jonathan Kimmitt who has been the driving force behind this release.

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lowRISC is a not-for-profit company using collaborative engineering to develop and maintain open source silicon designs and tools, through a unique combination of skills, expertise and vision.

We provide a home for multi-partner projects that deliver verified, high quality IP and tools, which provide the solid foundations that are necessary for the rapid development cycles required for next generation silicon products. lowRISC employs an engineering team in Cambridge, UK, working on our own developments, partner projects, and work-for-hire that is aligned with our mission.

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