The front-end server runs on the ARM side (PS) of the Zynq. It must be cross-compiled against the Xilinx SDK.

To compile your own front-end server:

# set up the RISCV environment variables
# set up the Xilinx environment variables
cd $TOP/riscv-tools/riscv-fesvr
mkdir build_fpga
cd build_fpga
../configure --host=arm-xilinx-linux-gnueabi
make -j$(nproc)

Once compilation has completed, you should find the following files:

ls -l fesvr-zedboard
ls -l

To copy your new front-end server to the FPGA image:

cd $TOP/fpga-zynq/zedboard
make ramdisk-open
sudo cp $TOP/riscv-tools/riscv-fesvr/build_fpga/fesvr-zedboard \
sudo cp $TOP/riscv-tools/riscv-fesvr/build_fpga/ \
make ramdisk-close
sudo rm -fr ramdisk

The proxy kernel (pk) used by the FPGA is the same one used in simulation. While not normally necessary, the proxy kernel can be recompiled using the following commands:

cd $TOP/fpga-zynq/zedboard
make ramdisk-open
sudo cp $TOP/riscv-tools/riscv-pk/build/pk ramdisk/home/root/pk
make ramdisk-close
sudo \rm -fr ramdisk