Interrupt Bridge

Passes interrupts lines from Earl Grey through to Sonata. Earl Grey controls which interrupt lines are sent.

Theory of Operations

A fixed subset of Earl Grey interrupt lines are connected into the interrupt bridge. There is an enable bit for each interrupt. When the interrupt is enabled it is sent through to Sonata. The pass through uses a simple masking scheme. When enabling an interrupt through the bridge if an interrupt is raised on the Earl Grey side it will be instantly raised on the Sonata side. Similarly when disabling an interrupt through the bridge whilst it is raised it will be instanatly dropped on the Sonata side.

When Earl Grey is donating a peripheral to Sonata and enabling the relevant interrupts on the bridge it is recommended interrupts are disabled at the peripheral to avoid Sonata receiving interrupts during the donation process. The expectation is Sonata will enable the interrupts it is interested in when the peripheral donation is complete. Similarly interrupts should be disabled at the peripheral when Sonata is releasing the donated peripheral back to Earl Grey.

Registers

Enable Register

Read-write

One bit per interrupt enable. Each register has 32 enable bits. The bit index within this register of an enable is Bridge ID % 32. The index of the register of an enable is Bridge ID / 32.

Register Offsets

Interrupt Mapping Table

This table provides a mapping from the Earl Grey PLIC IRQ IDs to the Interrupt Bridge IDs