By Stefan Wallentowitz and Wei Song

Release version 0.3 (07-2016)


lowRISC is a not-for-profit organisation whose goal is to produce a fully open source System-on-Chip (SoC) in volume. We are building upon RISC-V processor core implementations from the RISC-V team at UC Berkeley. We will produce a SoC design to populate a low-cost community development board and to act as an ideal starting point for derivative open-source and commercial designs.

In previous tutorials you can learn about tagged memory or how to run the design on an FPGA as an untethered system.

This tutorial adds further functionality towards the final SoC design by adding a debug infrastructure. It contains a technology preview of what we plan and gives some background on the trace debugging techniques. A demo is provided using a low-end Nexys™4 DDR Artix-7 FPGA Board.


  1. Overview of the debug infrastructure
  2. Prepare the environment
  3. Debug walkthrough
  4. Other
  5. Release notes

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