With the recent announcement of OpenTitan, we at lowRISC had many great conversations about the work we do to produce high-quality open source hardware and software. A great place to continue these discussions is the RISC-V Summit in San Jose, CA (Dec 10 – 12, 2019). lowRISC will showcase its work in the conference track and in the exhibit hall.
At booth 101, lowRISC will showcase its recent work and our engineers will be around to answer your questions. Stop by if you have questions about OpenTitan, lowRISC in general, or about the LLVM compiler work we’re doing!
If you’re using the LLVM compiler or are planning to use it for your next RISC-V project, we invite you to join Alex’s talk in the conference track. Titled “Production-ready RISC-V Support in LLVM/Clang 9.0 – How we Got There and What’s Next” the talk will retrace the journey to make the RISC-V LLVM backend production ready, an effort which hit a major milestone in August this year, when the RISC-V backend was enabled by default for all LLVM/Clang compiler builds.
See you there! And as always, if you cannot make it to the RISC-V Summit, just drop us a line at info@lowrisc.org!
Quick facts
- Production-ready RISC-V Support in LLVM/Clang 9.0 – How we Got There and What’s Next. Wednesday, 11 December 2019 1:20pm – 1:40pm, Grand Ballroom 220-C
- Find lowRISC in booth 101 in the exhibit hall.
Contact us
lowRISC is a not-for-profit company using collaborative engineering to develop and maintain open source silicon designs and tools, through a unique combination of skills, expertise and vision.
We provide a home for multi-partner projects that deliver verified, high quality IP and tools, which provide the solid foundations that are necessary for the rapid development cycles required for next generation silicon products. lowRISC employs an engineering team in Cambridge, UK, working on our own developments, partner projects, and work-for-hire that is aligned with our mission.