Tutorial for the v0.6 lowRISC release
By Jonathan Kimmitt (also see acknowledgements below)
Release version 0.6 (10-2018)
lowRISC is a not-for-profit organisation whose goal is to produce a secure, flexible, and fully open source System-on-Chip (SoC). We are building upon RISC-V processor core implementations from the RISC-V team at UC Berkeley. This aims to be the ideal starting point for derivative open source and commercial designs.
This tutorial adds further functionality towards the final SoC design:
- An eight packet buffer for Ethernet reception.
- Bare-metal GDB debugging over JTAG without any extra hardware.
- Processor speed doubled to 50MHz.
- Colour Console with proper PC-compatible keyboard events.
- Ethernet boot-loader DHCP support, ten times faster boot-loading.
- SD-Card boot-loader comprehensive card detection base on u-boot.
- Platform-level interrupt controller support.
- All peripheral data paths 64-bit width.
- Latest RISCV-kernel and Debian userland with advanced package tool.
The build environment and pre-built images support the same platform as the previous releases, a competitively priced Nexys™4 DDR Artix-7 FPGA Board.
|Rocket Priv. Spec.||?||?||1.7||nearly 1.91||nearly 1.91||1.10|
|Kernel md5 boot check||*||*||*|
|Debian binary compatible||*|
Work planned / In progress / TO DO
- Optimising card transfer speed / Implementing multi-block transfers.
- Offloading SD-card acceleration and Video scrolling to Minion.
- Wei Song was lead hardware developer up to v0.4
- Stefan Wallentowitz and Philipp Wagner provided the trace debug system (from v0.3)
- Furkan Turan provided the Zedboard patches
- Philipp Jantscher did the initial tagged memory port to debug-v0.3
- The Ethernet transceiver library is due to Alex Forencich (http://alexforencich.com/wiki/en/verilog/ethernet/readme). The preview version was translated from VHDL written by Philipp Kerling (https://github.com/pkerling/ethernet_mac)
- Palmer Dabbelt maintained the Linux kernel port to RISCV
- Andrew Waterman and a large team at SiFive developed the Rocket CPU
- Manuel Montecelo, Karsten Merker and Aurelien Jarno developed the Debian port to RISCV (https://wiki.debian.org/RISC-V#Creating_a_riscv64_chroot_from_a_merged_repository_with_debootstrap) and all assisted with debugging the bootstrap procedure on LowRISC.
- Rick Chen and the u-boot team provided the basis of the first stage MMC/SD boot loader