Tutorial for the v0.5 lowRISC preview release
By Jonathan Kimmitt, Wei Song and Alex Bradbury (also see acknowledgements below)
Release version 0.5 (12-2017)
lowRISC is a not-for-profit organisation whose goal is to produce a fully open source System-on-Chip (SoC) in volume. We are building upon RISC-V processor core implementations from the RISC-V team at UC Berkeley. We will produce a SoC design to populate a low-cost community development board and to act as an ideal starting point for derivative open-source and commercial designs.
This tutorial adds further functionality towards the final SoC design:
- A simple 100Mbps Ethernet capability.
- Remote booting via Ethernet from a Linux server.
- Preview of interrupt driven device drivers in Linux.
- Optimised SD-interface
- Console defaults to keyboard and optimised VGA-compatible text display.
- Network filing system (NFS) support in the RISCV kernel and NFS-root support scripts.
- Multiuser system leveraging the poky Linux build system.
The build environment and pre-built images support the same platform as the previous releases, a competitively priced Nexys™4 DDR Artix-7 FPGA Board.
|Rocket Priv. Spec.||?||?||1.7||nearly 1.91||nearly 1.91|
|Kernel md5 boot check||*||*|
- Overview of the Ethernet system
Work planned / In progress / TO DO
- Interfacing Pulpino (Minion) core to on-chip trace/debug bus.
- Programming Minion dynamically from Rocket under Linux.
- Optimising card transfer speed / Implementing multi-block transfers.
- GDB support under Linux.
- Revised interrupt handling block.
- Ethernet interfacing / booting / Linux support.
- Fully supporting tag instructions in compiler.
- Making tag support thread-safe / context switching safe.
- More security demos.
- Userland software running on the Rocket.
- Offloading SD-card acceleration and Video scrolling to Minion.
- Run-control debug for Rocket.
- Stefan Wallentowitz and Philipp Wagner provided the trace debug system
- Furkan Turan provided the Zedboard patches
- Philipp Jantscher did the initial tagged memory port to debug-v0.3
- The Ethernet transceiver library is due to Alex Forencich (http://alexforencich.com/wiki/en/verilog/ethernet/readme). The preview version was translated from VHDL written by Philipp Kerling (https://github.com/pkerling/ethernet_mac)