The lowRISC blog

GSoC Projects Successfully Completed

Time is ticking and summer is almost over already. With that, also our this years’ Google Summer of Code (GSoC) projects are coming to an end. A lot of open-source coding has been done, pull requests have been made, reviewed and merged. Experiments have been conducted, results were gathered, interpreted and presented. Bugs were found and fixed, and the resulting designs further improved. Both our students and mentors have been working hard and we are pleased to announce that both our two projects described below have been completed successfully.

GSoC Accepted Projects Announcement

We are pleased to announce that we will be mentoring two students as part of Google Summer of Code (GSoC). We are looking forward to working with Flavien and Yuichi on features and tools to improve IP such as Ibex, our open-source RISC-V core. Flavien Solt: Simulated Memory Controller It is a common pitfall to misinterpret or incorrectly scale performance numbers derived from benchmarks run on an FPGA-based SoC design.

Students for GSoC projects wanted

We are excited to be back as a mentoring organisation for Google Summer of Code (GSoC) and are currently looking for enthusiastic students interested in doing a project with us. The GSoC initiative gives students the opportunity to spend the summer break gaining real-world hardware and software development experience while earning a stipend from Google. If you’re a student interested in applying, we strongly recommend you read up on how GSoC works and study the Google Summer of Code Student Guide, which contains excellent advice on preparing a high quality proposal.

At FOSDEM you can hear how we made our Ibex CPU core faster

I’ll be giving a talk in the RISC-V devroom at FOSDEM on Saturday 1st February, in which I’ll describe how we are analysing and improving the performance of the Ibex RISC-V CPU core. I’ll discuss how Verilator is used to simulate Ibex running CoreMark and Embench and how I’ve analysed these simulations to identify major sources of stalls. This is used to inform what improvements should be made. Yosys was used to analyse the impact on area and clock frequency from these changes.

lowRISC 101: Introduction to lowRISC at the RISC-V Summit

With the recent announcement of OpenTitan, we at lowRISC had many great conversations about the work we do to produce high-quality open source hardware and software. A great place to continue these discussions is the RISC-V Summit in San Jose, CA (Dec 10 - 12, 2019). lowRISC will showcase its work in the conference track and in the exhibit hall. At booth 101, lowRISC will showcase its recent work and our engineers will be around to answer your questions.

Get started with OpenTitan

Interested in trying out the recently announced OpenTitan? We’ve put together a video that goes through an overview of how the OpenTitan prototype system is put together and how to get up and running with our pre-built release (providing simulator binaries and pre-built FPGA images for the Nexys Video Artix-7 board). It follows the steps from the OpenTitan Quickstart Guide. You can find out more about OpenTitan from our announcement blog and the OpenTitan website.

Announcing OpenTitan, the First Transparent Silicon Root of Trust

Today, we are excited to unveil the OpenTitan silicon root of trust (RoT) project, a new effort built using the successful collaborative engineering model created by lowRISC in partnership with Google and other commercial and academic partners. This effort sets a new bar for transparency in trusted silicon, and lowRISC is proud to serve as both steward and not-for-profit engineering contributor to OpenTitan, the world’s first open source silicon RoT.

lowRISC Collaborates with Industry Leaders to Create OpenTitan

Organisations aim to make the hardware root more transparent, trustworthy, and secure for everyone. CAMBRIDGE, England–(BUSINESS WIRE)–lowRISC C.I.C., the open source silicon and tools collaborative engineering company, today announced that it has partnered with ETH Zürich, Google, G+D Mobile Security, Nuvoton Technology and Western Digital in support of OpenTitan, an open source hardware root of trust (RoT) reference design and integration guidelines that enable chip producers and platform providers to build transparently implemented, high-quality hardware RoT chips tailored for data center servers and other devices.

Andy Hopper joins lowRISC CIC Board as Independent Chair

Today, we are delighted to announce that Professor Andy Hopper, CBE FRS FIET FREng, has joined the lowRISC Board of Directors as Independent Chair. “I’m delighted to be joining lowRISC CIC,” said Prof. Hopper, speaking today from Cambridge UK, “As digital systems pervade every aspect of our lives trust and transparency become crucial. An open source approach allows for public inspection of the principles and implementations being used. I believe the future of digital systems will be underpinned by not for profit organisations that provide design transparency and enable real innovation.

Introducing Greg & Tom

Greg Chadwick and Tom Roberts recently joined lowRISC’s growing engineering team. They’ve both taken some time to share a little about what they’re doing at lowRISC and what motivated them to join. Greg “It’s an exciting time to join the lowRISC team! Our Ibex core provides a solid foundation and clearly demonstrates the value of open source silicon, which I’m excited to be working on. My work so far has focused on the performance of Ibex; whilst it’s not intended as a high performance core there are various things we can do to improve it without major impact to area or power.