lowRISC is delighted that Andy Hopper, lowRISC’s independent chair, has been knighted for services to Computer Technology. Andy said “As you might imagine I am delighted. What I have achieved is all a result of teamwork. The University of Cambridge and the Cambridge Cluster have provided a wonderfully collaborative and flexible environment within which I have had the good fortune to work for over 40 years.” The culture he created, and his interest in and support for doing things in non-standard ways, has helped to establish over 200 start-ups, including lowRISC CIC.
The lowRISC blog
Last year, along with our partners, lowRISC announced OpenTitan, the world’s first open source silicon root of trust. The project has progressed rapidly since then. A recent Google Security Blog post detailed key milestones met, our growth in contributors, and revealed news of the first commercial OpenTitan tapeout. OpenTitan’s success demonstrates the value of the lowRISC collaborative engineering model, wherein our full-stack engineering team allows us to serve as an essential development hub.
On October 20th, lowRISC CIC won in the Open Hardware category at the 2020 OpenUK Awards, describing lowRISC as “the jewel in the crown of the UK’s open silicon companies”. The OpenUK awards promote “UK Leadership in Open Technology”, and are given out by OpenUK, a UK-based not-for-profit company which supports open source collaboration and open technologies within the United Kingdom. On receiving the award, lowRISC CTO, Alex Bradbury, said “We’re incredibly grateful to have been recognised for our achievements and contributions to date.
How we used differential testing to rapidly find and fix missed optimisation opportunities in LLVM's RISC-V backend
At this October 2020 LLVM Developers’ Meeting I presented a poster about how, with a surprisingly simple tool, we were able to rapidly identify, isolate, and fix a range of missed optimisation opportunities in LLVM’s RISC-V backend. The tool works by generating random C programs, compiling each program with both Clang and GCC (targeting RISC-V) and comparing the assembly generated by both compilers. If it estimates that Clang/LLVM generated worse code than GCC then it saves that case for further analysis.
Time is ticking and summer is almost over already. With that, also our this years’ Google Summer of Code (GSoC) projects are coming to an end. A lot of open-source coding has been done, pull requests have been made, reviewed and merged. Experiments have been conducted, results were gathered, interpreted and presented. Bugs were found and fixed, and the resulting designs further improved. Both our students and mentors have been working hard and we are pleased to announce that both our two projects described below have been completed successfully.
We are pleased to announce that we will be mentoring two students as part of Google Summer of Code (GSoC). We are looking forward to working with Flavien and Yuichi on features and tools to improve IP such as Ibex, our open-source RISC-V core. Flavien Solt: Simulated Memory Controller It is a common pitfall to misinterpret or incorrectly scale performance numbers derived from benchmarks run on an FPGA-based SoC design.
We are excited to be back as a mentoring organisation for Google Summer of Code (GSoC) and are currently looking for enthusiastic students interested in doing a project with us. The GSoC initiative gives students the opportunity to spend the summer break gaining real-world hardware and software development experience while earning a stipend from Google. If you’re a student interested in applying, we strongly recommend you read up on how GSoC works and study the Google Summer of Code Student Guide, which contains excellent advice on preparing a high quality proposal.
I’ll be giving a talk in the RISC-V devroom at FOSDEM on Saturday 1st February, in which I’ll describe how we are analysing and improving the performance of the Ibex RISC-V CPU core. I’ll discuss how Verilator is used to simulate Ibex running CoreMark and Embench and how I’ve analysed these simulations to identify major sources of stalls. This is used to inform what improvements should be made. Yosys was used to analyse the impact on area and clock frequency from these changes.
With the recent announcement of OpenTitan, we at lowRISC had many great conversations about the work we do to produce high-quality open source hardware and software. A great place to continue these discussions is the RISC-V Summit in San Jose, CA (Dec 10 - 12, 2019). lowRISC will showcase its work in the conference track and in the exhibit hall. At booth 101, lowRISC will showcase its recent work and our engineers will be around to answer your questions.
Interested in trying out the recently announced OpenTitan? We’ve put together a video that goes through an overview of how the OpenTitan prototype system is put together and how to get up and running with our pre-built release (providing simulator binaries and pre-built FPGA images for the Nexys Video Artix-7 board). It follows the steps from the OpenTitan Quickstart Guide. You can find out more about OpenTitan from our announcement blog and the OpenTitan website.