Tutorial for the debug preview of lowRISC

By Stefan Wallentowitz and Wei Song

Release version 0.3 (07-2016)

Introduction

lowRISC is a not-for-profit organisation whose goal is to produce a fully open source System-on-Chip (SoC) in volume. We are building upon RISC-V processor core implementations from the RISC-V team at UC Berkeley. We will produce a SoC design to populate a low-cost community development board and to act as an ideal starting point for derivative open-source and commercial designs.

In previous tutorials you can learn about tagged memory or how to run the design on an FPGA as an untethered system.

This tutorial adds further functionality towards the final SoC design by adding a debug infrastructure. It contains a technology preview of what we plan and gives some background on the trace debugging techniques. A demo is provided using a low-end Nexys™4 DDR Artix-7 FPGA Board.

Contents

1. Overview of the debug infrastructure

   • Debug interface
   • Debug modules
   • Debug software and methodology

2. Prepare the environment

   • Generic lowRISC setup
   • Open SoC Debug software

3. Debug walkthrough

   • Connecting to RTL simulation and enumeration
   • A debug session
   • Running on the FPGA

4. Other

   • SoC structure updates
   • How to add a new peripherial
   • Working with Zedboard

5. Release notes

   • Version 0.2: untethered lowRISC (12-2015)
   • Version 0.1: tagged memory (04-2015)

Other useful sources of information

• Open SoC Debug (Overview slides)